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CompuLab Ltd. FACE Modules – HW Specifications Page 14 of 63
Table 4 – EXT2 connector HOST side pinout
EXT-2 connector HOST side
Pin #
Pin Name
Signal Description
Pin #
Pin Name
Signal Description
A1
GND
Ground connection
B1
GND
Ground connection
A2
PEG_RX0+/RSVD0
Host CPU PEG_0 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
1
B2
PEG_TX0+/RSVD6
Host CPU PEG_0 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
1
A3
PEG_RX0-/RSVD1
B3
PEG_TX0-/RSVD7
A4
DGPU_PRSNT#/RS
VD3
Host chipset GPIO67, Input, PU-10k
B4
DGPU_PWREN#/RSVD8
Host chipset GPIO54, Output, PU-8.2k
A5
PEG_RX1+/RSVD4
Host CPU PEG_1 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
1
B5
PEG_TX1+/RSVD9
Host CPU PEG_1 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
1
A6
PEG_RX1-/RSVD5
B6
PEG_TX1-/RSVD10
A7
GND
Ground connection
B7
GND
Ground connection
A8
PEG_RX2+/RSVD1
1
Host CPU PEG_2 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B8
PEG_TX2+/RSVD16
Host CPU PEG_2 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A9
PEG_RX2-
/RSVD12
B9
PEG_TX2-/RSVD17
A10
DGPU_PWROK/RS
VD13
Host chipset GPIO17, Input/Output, PD-10k
B10
DGPU_HOLD_RST#/RS
VD18
Host chipset GPIO50, Output, PU-8.2k
A11
PEG_RX3+/RSVD1
4
Host CPU PEG_3 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B11
PEG_TX3+/RSVD19
Host CPU PEG_3 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A12
PEG_RX3-
/RSVD15
B12
PEG_TX3-/RSVD20
A13
GND
Ground connection
B13
GND
Ground connection
A14
PEG_RX4+/RSVD2
1
Host CPU PEG_4 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B14
PEG_TX4+/RSVD26
Host CPU PEG_4 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A15
PEG_RX4-
/RSVD22
B15
PEG_TX4-/RSVD27
A16
DGPU_SELECT#/R
SVD23
Host chipset GPIO52, Output, PU-8.2k
B16
DGPU_HPD_INTR#/RSV
D28
Host chipset GPIO6, Input, PU-10k
A17
PEG_RX5+/RSVD2
4
Host CPU PEG_5 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B17
PEG_TX5+/RSVD29
Host CPU PEG_5 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A18
PEG_RX5-
/RSVD25
B18
PEG_TX5-/RSVD30
A19
V5SBY
5V power domain
B19
V5SBY
5V power domain
A20
PEG_RX6+/RSVD3
1
Host CPU PEG_6 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B20
PEG_TX6+/RSVD36
Host CPU PEG_6 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A21
PEG_RX6-
/RSVD32
B21
PEG_TX6-/RSVD37
A22
DGPU_PWM_SELE
CT#/RSVD33
Host chipset GPIO53, Output, No pull
B22
SPARE/eDP_HDP
NC
A23
PEG_RX7+/RSVD3
4
Host CPU PEG_7 (x8) - PCIe Gen3 (up to
8Gbps) differential receive pair for external
graphics
2
B23
PEG_TX7+/RSVD38
Host CPU PEG_7 (x8) - PCIe Gen3 (up to
8Gbps) differential transmit pair for
external graphics
2
A24
PEG_RX7-
/RSVD35
B24
PEG_TX7-/RSVD39
A25
GND
Ground connection
B25
GND
Ground connection
A26
LVDS_A0+/eDP_T
X0+
LVDS Channel A differential pair 0 Host data
output
3
B26
PEG_CLK+/RSVD40
Host PEG CLK output differential pair -
100MHz PCIe Gen2 to PCIe Graphics
device
A27
LVDS_A0-
/eDP_TX0-
B27
PEG_CLK-/RSVD41
A28
LVDS_A1+/eDP_T
X1+
LVDS Channel A differential pair 1 Host data
output
3
B28
LVDS_BKLT_CTRL
Panel Backlight Brightness Control
3
A29
LVDS_A1-
/eDP_TX1-
B29
COM1_DCR
Full RS232 interface from Host to DCE
device
A30
LVDS_A2+/eDP_T
X2+
LVDS Channel A differential pair 2 Host data
output
3
B30
COM1_TX
A31
LVDS_A2-
/eDP_TX2-
B31
COM1_DCD
A32
GND
Ground connection
B32
GND
Ground connection
- FACE Modules 1
- Legal Notice 2
- Revision History 3
- Table of Contents 4
- Table of Figures 8
- Table of Tables 8
- 1 Overview 10
- 1.3 FACE Module Interface 11
- 1.3.1 Connectors Specs 11
- 1.3.2 Connectors Pinout 12
- EXT-2 connector HOST side 14
- 1.4 Layout 16
- 2.3 Block Diagram 18
- 2.1 Description 18
- 2.2 Highlights 18
- 2.4 Mechanics 19
- 2.4.1 PCB Assembly 19
- 2.4.2 Front Panel 19
- 3.1 Description 20
- 3.2 Highlights 20
- 3.3 Block Diagram 20
- 3.4 Hardware Specifications 21
- 3.4.1 mSATA slot 21
- 3.5 Mechanics 22
- 3.5.1 PCB Assembly 22
- 3.5.2 Front Panel 22
- 3.6 Software Drivers 23
- 4.1 Description 24
- 4.2 Highlights 24
- 4.3 Block Diagram 25
- 4.4 Hardware Specifications 26
- 4.4.5 RJ-11 Serial Ports 28
- 4.4.6 RJ-45 CAN Bus Pinout 28
- 4.5 Configuration 29
- 4.5.2 CAN Bus power supply 29
- 4.6 Mechanics 30
- 4.6.1 PCB Assembly 30
- 4.6.2 Front Panel 30
- 4.7 Software Drivers 31
- 5.1 Description 32
- 5.2 Highlights 32
- 5.3 Block Diagram 32
- 5.4 Hardware Specifications 33
- 5.5 Mechanics 34
- 5.5.1 PCB Assembly 34
- 5.5.2 Front Panel 34
- 5.6 Software Drivers 35
- / FACE Module interface 36
- 6.4 Hardware Specifications 37
- 6.4.3 SPI NOR Flash 38
- 6.5 Mechanics 39
- 6.5.1 PCB Assembly 39
- 6.5.2 Front Panel 39
- 6.6 Software Drivers 40
- 7.4 Hardware Specifications 42
- 7.4.1 Mini PCI Express Slot 42
- 7.5 Mechanics 43
- 7.5.1 PCB Assembly 43
- 7.5.2 Front Panel 43
- 8.1 Description 44
- 8.2 Highlights 44
- 8.3 Block Diagram 45
- 8.4 Hardware Specifications 46
- 8.4.7 RJ11 Connector Pinout 50
- 8.5 Cables 51
- 8.5.2 RJ11 to DB9 Cable 52
- 8.6 Mechanics 53
- 8.6.1 PCB Assembly 53
- 8.6.2 Front Panel 54
- 8.7 Software Drivers 55
- PI6C20400 56
- 1:4 Clock Driver 56
- CML differential 56
- PSE High Voltage 56
- 10.3.4 SPI NOR Flash 59
- Table 13 – PoE RJ45 pinout 60
- 10.4 Mechanics 61
- 10.4.1 PCB Assembly 61
- 10.4.2 Front Panel 61
- 10.5 Software Drivers 62
- 10.6 Safety Information 62
- 11 Reference 63
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