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CompuLab Ltd. FACE Modules – HW Specifications Page 34 of 63

5.4.2 IDT ICS9DB102 1-to-2 Differential Clock Driver

IDT ICS9DB102 is two output clock buffer for PCIe Gen1 & Gen2 with HCSL current mode differential

outputs.

Device zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a

differential compliant input clock. It attenuates jitter on the input clock and has a selectable PLL Band

Width to maximize performance in systems with or without Spread-Spectrum clocking.

5.5 Mechanics

5.5.1 PCB Assembly

Figure 16 – FM-XTDEU2/4 PCB Assembly Top

5.5.2 Front Panel

Figure 17 – FM-XTDEU2/4 front panel drawing

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 62 63

FACE Modules 1
Legal Notice 2
Revision History 3
Table of Contents 4
Table of Figures 8
Table of Tables 8
1 Overview 10
1.3 FACE Module Interface 11
1.3.1 Connectors Specs 11
1.3.2 Connectors Pinout 12
EXT-2 connector HOST side 14
1.4 Layout 16
2.3 Block Diagram 18
2.1 Description 18
2.2 Highlights 18
2.4 Mechanics 19
2.4.1 PCB Assembly 19
2.4.2 Front Panel 19
3.1 Description 20
3.2 Highlights 20
3.3 Block Diagram 20
3.4 Hardware Specifications 21
3.4.1 mSATA slot 21
3.5 Mechanics 22
3.5.1 PCB Assembly 22
3.5.2 Front Panel 22
3.6 Software Drivers 23
4.1 Description 24
4.2 Highlights 24
4.3 Block Diagram 25
4.4 Hardware Specifications 26
4.4.5 RJ-11 Serial Ports 28
4.4.6 RJ-45 CAN Bus Pinout 28
4.5 Configuration 29
4.5.2 CAN Bus power supply 29
4.6 Mechanics 30
4.6.1 PCB Assembly 30
4.6.2 Front Panel 30
4.7 Software Drivers 31
5.1 Description 32
5.2 Highlights 32
5.3 Block Diagram 32
5.4 Hardware Specifications 33
5.5 Mechanics 34
5.5.1 PCB Assembly 34
5.5.2 Front Panel 34
5.6 Software Drivers 35
/ FACE Module interface 36
6.4 Hardware Specifications 37
6.4.3 SPI NOR Flash 38
6.5 Mechanics 39
6.5.1 PCB Assembly 39
6.5.2 Front Panel 39
6.6 Software Drivers 40
7.4 Hardware Specifications 42
7.4.1 Mini PCI Express Slot 42
7.5 Mechanics 43
7.5.1 PCB Assembly 43
7.5.2 Front Panel 43
8.1 Description 44
8.2 Highlights 44
8.3 Block Diagram 45
8.4 Hardware Specifications 46
8.4.7 RJ11 Connector Pinout 50
8.5 Cables 51
8.5.2 RJ11 to DB9 Cable 52
8.6 Mechanics 53
8.6.1 PCB Assembly 53
8.6.2 Front Panel 54
8.7 Software Drivers 55
PI6C20400 56
1:4 Clock Driver 56
CML differential 56
PSE High Voltage 56
10.3.4 SPI NOR Flash 59
Table 13 – PoE RJ45 pinout 60
10.4 Mechanics 61
10.4.1 PCB Assembly 61
10.4.2 Front Panel 61
10.5 Software Drivers 62
10.6 Safety Information 62
11 Reference 63

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