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CompuLab Ltd. FACE Modules – HW Specifications Page 49 of 63

8.4.3 IDT ICS9DB102 1-to-2 Differential Clock Driver

IDT ICS9DB102 is two output clock buffer for PCIe Gen1 & Gen2 with HCSL current mode differential

outputs.

Device zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a

differential compliant input clock. It attenuates jitter on the input clock and has a selectable PLL Band

Width to maximize performance in systems with or without Spread-Spectrum clocking.

8.4.4 MAX3221 RS232 Transceiver

 Single-channel RS232 serial protocol transceiver

 Implementation RS232 PHY serial protocol port

 Data rate of 250kbps or more

 Low power operation and auto-shutdown

8.4.5 ADM3491 RS422/RS485 Transceiver

 Single-channel RS422/RS485 serial protocol transceiver

 Implements RS422/RS485 PHY serial protocol

 Supports full-duplex RS485 protocol with data rate of up to 10Mbps

 Low power operation and auto-shutdown

8.4.6 DB15 Connectors Pinout

Table 10 – DB15 Connector Pinout

Pin #

Type

Functionality

Cable Connector

P1 - 1

Analog Input

Audio 1

AI01

P1 - 2

Analog Input

Audio 2

AI02

P1 - 3

GND

P1 - 4

Analog Input

Audio 3

AI03

P1 - 5

Analog Input

Audio 4

AI04

P1 - 6

Analog Input

Video 1A

VI11

P1 - 7

Analog Input

Video 2D

VI12

P1 - 8

GND

P1 - 9

Analog Input

Video 3A

VI13

P1 - 10

Analog Input

Video 4D

VI14

P1 - 11

Analog Input

Video 1B

VI21

P1 - 12

Analog Input

Video 2C

VI22

P1 - 13

GND

P1 - 14

Analog Input

Video 3B

VI23

P1 - 15

Analog Input

Video 4C

VI24

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 62 63

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