CompuLab IPC2 Bedienungsanleitung Seite 15

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CompuLab Ltd. FACE Modules HW Specifications Page 15 of 63
A33
LVDS_A3+/eDP_T
X3+
LVDS Channel A differential pair 3 Host data
output
3
B33
COM1_DTR
Full RS232 interface from Host to DCE
device
A34
LVDS_A3-
/eDP_TX3-
B34
COM1_RTS
A35
LVDS_VDD_EN
LVDS Panel Power Enable
3
B35
COM1_RX
A36
LVDS_ACLK+/eDP
_AUX+
LVDS Channel A differential pair Host clock
output
3
B36
COM1_CTS
A37
LVDS_ACLK-
/eDP_AUX-
B37
COM1_RI
A38
GND
Ground connection
B38
LVDS_BKLT_EN
LVDS Backlight Enable
3
A39
LVDS_CTRL_CLK
LVDS Control interface for external SSC clock
chip (I2C based). Optional.
3
B39
LVDS_I2C_CLK
LVDS DDC (I2C based) management
interface. EDID support for flat panel
display
3
A40
LVDS_CTRL_DATA
B40
LVDS_I2C_DAT
A41
PEG_CLK_REQ#/R
SVD42
Clock Request Signal for PCIe Graphics (PEG)
B41
GND
Ground connection
A42
RESERVED
Reserved
B42
RESERVED
Reserved
A43
RESERVED
B43
RESERVED
A44
GND
Ground connection
B44
NC
NC
A45
RESERVED
Reserved
B45
RESERVED
Reserved
A46
RESERVED
B46
RESERVED
A47
USB_OC_4_5#
USB Overcurrent Indicator for lanes 2/3
B47
SPARE0
Host chipset spare GPIO
A48
USB4_P
USB Host interface 4
B48
VCC_12V
Main 12V power domain
A49
USB4_N
B49
VCC_12V
A50
GND
Ground connection
B50
VCC_12V
Notes:
1. Merged with PCI Express signals to Mini PCIe card on fit-PC3/3i
2. GPIOs on fit-PC3/3i
3. Fit-PC3/3i design does not feature LVDS interface
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