
CompuLab Ltd. FACE Modules – HW Specifications Page 15 of 63
LVDS Channel A differential pair 3 Host data
output
3
Full RS232 interface from Host to DCE
device
LVDS Panel Power Enable
3
LVDS Channel A differential pair Host clock
output
3
LVDS Control interface for external SSC clock
chip (I2C based). Optional.
3
LVDS DDC (I2C based) management
interface. EDID support for flat panel
display
3
Clock Request Signal for PCIe Graphics (PEG)
USB Overcurrent Indicator for lanes 2/3
Notes:
1. Merged with PCI Express signals to Mini PCIe card on fit-PC3/3i
2. GPIOs on fit-PC3/3i
3. Fit-PC3/3i design does not feature LVDS interface
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